This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits include circuitry to perform monitoring functions to assist with preserving a logical state. For instance, FIG. 1 shows a conventional keeper circuit 100 for memory. In this circuit 100, when memory goes into read, a pre-charge 124 is cut-off (prech_top), and a bitline 110 (e.g., rbl/bl/gbl) will be floating high. Due to many bit cells (not shown) in memory, the bitline 110 will drop over time, even when the bitline 110 is not programmed to drop. Typically, due to leakage, the bitline 110 may provide a wrong bit value. Further, leaky conditions, such as, e.g., high temperature, leaky process corner, number of bit cells, and some non-physical parameters, such as, e.g., added margin in simulations, may speed up bitline 110.
For many years, to avoid unwanted bitline drop, the conventional keeper 100 was used with a P-type Metal-Oxide-Semiconductor (PMOS) Pfb2 that is (substantially) weak so as to reduce its strength. In this configuration, the PMOS keeper Pfb2 compensates for the leakage. However, this does not track well over technology corners, voltages, and/or temperature ranges. In conventional technology, PMOS strength was varied to compensate for varying leakage. From process sizes of 40 nm and smaller, varying length is no longer applicable, and in these situations, designers compensate for this issue by stacking the keeper with multiple PMOS transistors in series, and counting on back-bias effects, which made these devices even weaker. In modern fin technologies, designers may use up to 5-6 PMOS transistors in series to achieve an overall weak PMOS transistor. In these situations, designers typically rely on series resistance of these series components instead of relying on transistor characteristics. It has been suggested to use a strong PMOS transistor to compensate for leakage. However, in these situations, during a read of a ‘0’ (zero), the bitline 110 voltage should drop, and any PMOS transistor in the bitline path that hinders this voltage drop may significantly delay memory read-out. As such, there exists a need for a more effective keeper that improves power, performance and area (PPA) and/or voltage range of an integrated circuit.